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| CY2CC910 1:10 Clock Fanout Buffer Features Description The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industry's fastest logic and buffers. The Cypress CY2CC910 fanout buffer features one input and 10 outputs. It is ideal for conversion from and to 3.3V, 2.5V, and 1.8V Designed for Data Communications clock management applications, the large fanout from a single input reduces loading on the input clock. Cypress employs the unique AVCMOS type outputs VOI (Variable Output Impedance) that dynamically adjust for variable impedance matching, eliminate the need for series damping resistors, and reduce overall noise. Low voltage operation Full range support: 3.3V 2.5V 1.8V Over voltage tolerant input hot swappable 1:10 Fanout Drives either a 50-Ohm or 75-Ohm load Low input capacitance Low output skew Low propagation delay Typical (tpd less than 4 ns) High speed operation: 200 MHz at1.8V 650 MHz at 2.5V and 3.3V Industrial versions available Available packages include: SOIC, SSOP Logic Block Diagram 3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) 5 VDD 4 ,8 1 5 ,2 0 IN 1 7 9 11 INPUT (AVCMOS) 2 ,6 ,1 0 1 3 ,1 7 12 14 GND 16 18 19 Cypress Semiconductor Corporation Document #: 38-07348 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 22, 2008 [+] Feedback CY2CC910 Pin Configuration Figure 1. 20-Pin SOIP-SSOP IN GND Q1 VDD Q2 GND Q3 VDD Q4 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 20 pin SOIC/SSOP Pin Description Pin Number 1 2,6,10,13,17 4,8,15,20 3,5,7,9,11,12,14,16,18,19 IN Pin Name Input Ground Power Supply Output Description GND VDD Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 Maximum Ratings[1] Storage Temperature: ................................. -65C to +150C Ambient Temperature: .................................. -40C to +85C Supply Voltage to Ground Potential VCC ...................................................................-0.5V to 4.6V Input..................................................................-0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................... -0.5V to VDD + 1V DC Output Voltage.................................... -0.5V to VDD + 1V Power Dissipation........................................................ 0.75W Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07348 Rev. *C CY2CC910 Page 2 of 11 [+] Feedback CY2CC910 Variable Output Impedance Control (VOI) Figure 2. Output Voltage versus Output Current (TA = 25C) Pull Down 3.5 Pull Up 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 Iol (A) Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V Vdd = 3.3 V Ioh (A) Vdd = 2.5 V Vdd = 1.8 V DC Electrical Characteristics At 3.3V (See Figure 3) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL IOH = -12 mA VDD = Min., VIN = VIH or VIL IOL = 12 mA Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 -0.7 VIN = 2.7V VIN = 0.5V Min 2.3 2 Typ 3.3 0.2 0.5 5.8 0.8 1 -1 20 -1.2 -50 100 Max Unit V V V V A A A V mA A mV Document #: 38-07348 Rev. *C Page 3 of 11 [+] Feedback CY2CC910 At 2.5V (See Figure 3) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power Down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 -0.7 VIN = 2.4V VIN = 0.5V IOH = -7 mA IOH = 12 mA IOL = 12 mA 1.6 Min 1.8 1.6 0.65 5.0 0.8 1 -1 20 -1.2 -50 100 Typ Max Unit V V V V V A A A V mA A mV At 1.8V (See Figure 7) Parameter VDD VIH VIL VOH VOL Description Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = -2 mA IOH = 2 mA Test Condition[2] Min 1.71 0.65VDD[1.1] -0.3 VDD - 0.45[1.2] 0.45 Max 1.89 4.3 0.35 VDD[0.6] Unit V V V V V Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Typ 2.5 6.5 Max Unit pF pF Power Supply Characteristics (See Figure 3) Parameter ICC ICCD IC Description Delta ICC Quiescent Power Supply Current Dynamic Power Supply Current Total Power Supply Current Test Conditions (IDD @ VDD = Max and VIN = VDD) - (IDD @ VDD = Max and VIN = VDD - 0.6V) VDD = Max Input toggling 50% Duty Cycle, Outputs Open VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Min Typ Max 50 0.63 Unit A mA/ MHz mA 25 Note 2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. Document #: 38-07348 Rev. *C Page 4 of 11 [+] Feedback CY2CC910 High Frequency Parametrics Parameter DJ Fmax 3.3V Description Jitter, Deterministic Test Conditions 50% duty cycle tW(50-50) The "point to point load circuit" | Output Jitter - Input Jitter | 50% duty cycle tW(50-50) Standard Load Circuit. 50% duty cycle tW(50-50) The "point to point load circuit" Fmax 2.5V Fmax 1.8V Fmax(20) tW 3.3V tW 2.5V tW 1.8V Maximum frequency VDD = 2.5V Maximum frequency VDD = 1.8V Maximum frequency VDD = 3.3V Minimum pulse VDD = 3.3V Minimum pulse VDD = 2.5V Minimum pulse VDD = 1.8V The "point-to-point load circuit" VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The "6-pF load circuit" VIN = 1.7/0.0V VOUT = 1.2V/0.4V 20% duty cycle tW(20-80) The "point to point load circuit" VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The "point-to-point load circuit" VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V The "point-to-point load circuit" VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V The "6-pF load circuit" VIN = 1.7V/0.0V VOUT = 1.2V/0.4V See Figure 5 Min Typ Max 20 Unit ps Maximum frequency VDD = 3.3V See Figure 3 See Figure 5 See Figure 5 See Figure 7 See Figure 6 160 650 200 200 250 MHz MHz MHz MHz See Figure 5 1 ns See Figure 5 1 ns See Figure 7 1 ns AC Switching Characteristics At 3.3V (VDD = 3.3V 5%, Temperature = -40C to +85C) Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase). Pulse Skew: Skew between opposite transitions of the same output (tPHL - tPLH). See Figure 11 See Figure 10 Description See Figure 4 Min 1.5 1.5 Typ 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max 3.5 3.5 Unit ns ns V/ns V/ns ns ns ns Package Skew: Skew between outputs of different packages at See Figure 12 the same power supply voltage, temperature and package type. At 2.5V (VDD = 2.5V 5%, Temperature = -40C to +85C) Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase). See Figure 11 Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 10 - tPLH). Package Skew: Skew between outputs of different packages at the same See Figure 12 power supply voltage, temperature and package type. Description See Figure 4 Min 1.5 1.5 Typ 2.7 2.7 0.8 0.8 0.2 0.2 0.4 Max Unit 3.5 3.5 ns ns V/ns V/ns ns ns ns Document #: 38-07348 Rev. *C Page 5 of 11 [+] Feedback CY2CC910 AC Switching Characteristics At 1.8V(VDD = 1.8V 5%, Temperature = -40C to +85C) Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Description Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time 20 - 80% Output Fall Time 20 - 80% Output Skew: Skew between outputs of the same package (in phase). Pulse Skew: Skew between opposite transitions of the same output (tPHL - tPLH). Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. See Figure 8 Min 1.5 1.5 0.2 0.2 Typ Max Unit 2.7 3.5 ns 2.7 3.5 ns 1.5 ns 1.5 ns 0.2 ns 0.2 0.4 ns ns See Figure 11 See Figure 10 See Figure 12 Parameter Measurement Information: VDD at 3.3V to 2.5V Figure 3. Load Circuit [3,4,5] Figure 5. Point to Point Load Circuit[3,4,5] From Output Under Test C L = 50 pF 500 ohm From Output Under Test CL = 3 pF 500 ohm Figure 4. Voltage Waveforms Propagation Delay Times[6] 0.8VDD Figure 6. Voltage Waveforms - Pulse Duration[4] tw(50-50) Input VDD/2 VDD/2 0V 0.8VDD Input tPLH Output VDD/2 VDD/2 0V tPHL VDD/2 VDD/2 VOH VOL tw(20-80) Input VDD/2 0.8VDD 0V Document #: 38-07348 Rev. *C Page 6 of 11 [+] Feedback CY2CC910 Parameter Measurement Information: VDD at 8V Figure 7. Load Circuit [3,4,5] Figure 9. Voltage Waveforms - Pulse Duration[4] tw(50-50) Input 0.9V 0.9V 0V tw(20-80) Input 0.9V 0V 1.8V From Output Under Test CL = 6 pF 500 ohm 1.8V Figure 8. Voltage Waveforms Propagation 1.8V Figure 10. Pulse Skew - tsk(p) 3V Input tPLH Output 0.9V 0.9V 0V tPHL INPUT tPLH tPHL 1.5V 0V VOH 1.5V VOL tsk(P) = l tPHL - tPLH l 0.9V 0.9V VOH VOL OUTPUT Figure 11. Output Skew - tsk(0) 3V 1.5V INPUT tPLH1 tPHL1 0V VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V VOL OUTPUT 2 tPLH 2 tPLH 2 tsk (P) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Notes 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50, tR < 2.5 ns, tF < 2.5 ns. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd. Document #: 38-07348 Rev. *C Page 7 of 11 [+] Feedback CY2CC910 Figure 12. Package Skew - tsk(t) 3V 1.5V INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V VOL PACKAGE 2 OUTPUT tPLH 2 tPLH 2 tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Ordering Information Part Number CY2CC910SI CY2CC910SIT CY2CC910SC CY2CC910SCT CY2CC910OI CY2CC910OIT CY2CC910OC CY2CC910OCT Pb-free CY2CC910OXI CY2CC910OXIT CY2CC910OXC CY2CC910OXCT Package Type 20-pin SOIC 20-pin SOIC-Tape and Reel 20-pin SOIC 20-pin SOIC-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel Product Flow Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0C to 70C Commercial, 0C to 70C Status Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0C to 70C Commercial, 0C to 70C Active Active Active Active Document #: 38-07348 Rev. *C Page 8 of 11 [+] Feedback CY2CC910 Package Drawing and Dimensions Figure 13. 20-Pin (300-Mil) SOIC S5 (51-85024) 51-85024 *C Document #: 38-07348 Rev. *C Page 9 of 11 [+] Feedback CY2CC910 Figure 14. 20-Pin Shrunk Small Outline Package O20 51-85077-*C Document #: 38-07348 Rev. *C Page 10 of 11 [+] Feedback CY2CC910 Document History Page Document Title: CY2CC910 1:10 Clock Fanout Buffer Document No: 38-07348 Rev. ECN NO. Orig. of Change Submission Date Description of Change ** *A 114318 119148 TSM RGL 05/10/02 10/07/02 New Data Sheet Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table. Added Lead-free devices for SSOP Added "Status" column to Ordering Information table Updated Package Diagram 51-85024 Updated template *B *C 404287 2595534 RGL CXQ/PYRS See ECN 10/23/08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07348 Rev. *C Revised October 22, 2008 Page 11 of 11 All products and company names mentioned in this document may be trademarks of their respective holders. [+] Feedback |
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